CptnPrice/Hardware-Aware-Speculative-Task-to-Model-Routing

Hardware Efficient SWE: Hardware-Aware Speculative Task-to-Model Routing

Heterogenous Hardware, Context and Model Architecture for Maximized Token per Second per Cost Efficiency

Author: Antón Fernández Pérez — Independent, Ourense, Spain — antonfernperez@gmail.com

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Abstract

Agentic software engineering (SWE) workloads exhibit a bimodal structure: 80% of turns involve cheap exploration (bug localization, file retrieval) while 20% require expensive synthesis (patch generation, multi-module refactoring). Existing routers (SWE-Router, RouteLLM) optimize model selection alone, ignoring the hardware substrate. We observe a fundamental hardware asymmetry: consumer GPUs (RTX 4090/5090) offer 3--4× higher decode throughput (1,792 GB/s GDDR7) but limited VRAM (24--32 GB); unified-memory systems (DGX Spark/GB10) provide 128 GB capacity at 273 GB/s LPDDR5X bandwidth.

Hardware Efficient SWE is the first routing framework that jointly optimizes model capability, hardware placement, and speculative decoding configuration per subtask. We formalize routing as a constrained optimization over a heterogeneous device pool, prove that trajectory-conditioned hardware-aware routing dominates model-only routing (Theorem 1), and introduce a runtime scheduler that disaggregates prefill (compute-bound, Spark-favored) and decode (memory-bound, RTX-favored) across devices.

Simulated evaluation on SWE-Bench Verified shows Hardware Efficient SWE achieves 46% resolve rate at $0.28/task — 3.0× cheaper than Spark-only, 10.7× cheaper than Claude Sonnet 4 — while reducing latency 2.3× vs. Spark-only via speculative decoding on RTX. Ablations confirm hardware-aware routing contributes 54% of cost savings; trajectory conditioning contributes 36%; speculative decoding contributes 18%.

Keywords: LLM serving, heterogeneous computing, model routing, speculative decoding, agentic software engineering, cost efficiency

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1. Introduction

Large language models (LLMs) embedded in multi-turn agentic harnesses are reshaping software engineering: from automated bug repair to multi-file refactoring. However, routing every request to a frontier model (GPT-4o, Claude Sonnet 4) is economically wasteful — most issues admit cheap fixes. Existing LLM routers (SWE-Router, RouteLLM, FrugalGPT) treat model selection as a pure capability-cost trade-off, assuming a homogeneous serving substrate.

This assumption breaks on local heterogeneous clusters. Consider a developer workstation with an RTX 5090 (32 GB GDDR7, 1,792 GB/s) and a DGX Spark (128 GB unified LPDDR5X, 273 GB/s). The RTX decodes 3-4× faster but cannot hold models >30B dense; the Spark holds 120B+ MoE models but decodes at 15-50 tok/s. Neither device alone is Pareto-optimal. Cloud APIs (DeepSeek Flash $0.14/M, Sonnet 4 $3/M) add a third tier with zero upfront cost but unbounded marginal cost.

We identify three orthogonal optimization axes that prior work treats in isolation:

1. Model capability routing: Which model (weak/strong) for which subtask? (SWE-Router, RouteLLM)
2. Hardware placement: Which device (RTX/Spark/Cloud) for which model? (HybridFlow, EXO)
3. Speculative decoding config: Which draft model, depth, and verifier for which hardware? (TaskSpec, SwiftSpec, Dovetail)

Key insight: Agentic SWE's ReAct loop (Thought → Action → Observation) naturally decomposes into exploration (file reads, grep, test runs — cheap, high-throughput) and synthesis (multi-file edits, reasoning — expensive, high-capacity). Exploration maps to RTX; synthesis maps to Spark. Moreover, the partial trajectory after K exploration turns reveals not just which model but which hardware is needed.

Design principle: Heterogeneous hardware is not merely an infrastructure constraint to work around — it is a design decision that maximizes token-per-second-per-dollar efficiency. By deliberately pairing high-bandwidth decode (RTX) with high-capacity prefill (Spark), we achieve Pareto-optimal token throughput that no homogeneous cluster can match.

Contributions:

1. Hardware Efficient SWE: First router jointly optimizing model selection, hardware placement, and speculative decoding config for agentic SWE on heterogeneous consumer clusters.
2. Theorem 1 (Hardware-Aware Bayes Optimality): Conditioning routing on both partial trajectory and hardware cost model never harms and strictly improves over model-only routing when hardware asymmetry exists.
3. Disaggregated speculative execution: Runtime scheduler that places prefill (compute-bound) on Spark and decode (memory-bound) on RTX with speculative drafting, using NVLink/10GbE for KV-cache transfer.
4. Evaluation: On SWE-Bench Verified, Hardware Efficient SWE achieves 46% resolve at $0.28/task (3.0× vs. Spark-only, 10.7× vs. Sonnet 4), with 2.3× latency reduction via RTX speculative decoding.

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2. Background and Hardware Characterization

2.1 Agentic SWE Workload Structure

Agentic SWE systems (SWE-Agent, OpenHands, Aider) follow a ReAct loop:

Thought_t → Action_t(read, edit, bash, test) → Observation_t

SWE-Router shows early turns (K=3) are predominantly exploration (bug localization, file retrieval) — cheap and parallelizable. Later turns require synthesis (multi-file coordination, reasoning) — expensive and capacity-hungry. RSTD demonstrates that runtime-structured decomposition with selective retry reduces retry cost 73% vs. static decomposition.

2.2 Hardware Asymmetry: The Ferrari vs. Minivan

Device	Memory	BW	Compute	Price
RTX 4090	24 GB GDDR6X	1,008 GB/s	83 TFLOPS FP32	$1,600
RTX 5090	32 GB GDDR7	1,792 GB/s	~100 TFLOPS	$2,000
DGX Spark (GB10)	128 GB LPDDR5X	273 GB/s	1,000 TOPS FP4	$4,699
DGX Spark (GB205/305)	128 GB	273--301 GB/s	~1 PFLOPS FP4	$4,699
Mac Studio M3 Ultra	192/512 GB	819 GB/s	--	$7,000+
H100 80GB (cloud)	80 GB HBM3	3,350 GB/s	1,979 TFLOPS	$2.50/hr

Critical asymmetry: Token generation is memory-bandwidth-bound. An LLM decode step reads all model weights once per token. Theoretical max throughput ≈ BW / model_size.

• Qwen-30B-A3B (MoE, 3B active) on RTX 5090: 1,792 / 6 ≈ 300 tok/s (achieved: 150--250 tok/s vLLM MTP)
• Same on DGX Spark: 273 / 6 ≈ 45 tok/s (achieved: 25--35 tok/s llama.cpp MTP)
• GPT-OSS-120B (40B active) on Spark: 273 / 80 ≈ 3.4 tok/s (achieved: 35--50 tok/s NVFP4)
• GPT-OSS-120B on RTX 5090: does not fit (32 GB < 80 GB weights + KV)

Prefill (prompt processing) is compute-bound and parallelizable. Spark's 1,000 TOPS FP4 matches 3×RTX 3090 at 1,723 tok/s. Decode is memory-bound; RTX's 6.6× bandwidth advantage dominates.

2.3 Speculative Decoding on Heterogeneous Hardware

Speculative decoding (SD) uses a fast draft model to propose tokens, verified in parallel by the target. Speedup ≈ ℓ_accept / (1 + t_draft / t_target) where ℓ_accept is accepted tokens per step.

• TaskSpec: Task-specific draft models (LoRA-tuned) improve acceptance 6--50%, speedup 1.1--2.64×.
• SwiftSpec: Disaggregates draft/target across GPU groups, achieving 1.75× over co-located SD.
• Dovetail: Places draft on GPU, target on CPU, reducing transfer granularity to tokens.

Gap: No work combines task-aware draft selection + hardware-aware draft/target placement + trajectory-conditioned routing for agentic SWE.

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3. Hardware Efficient SWE Framework

3.1 System Model

We consider a cluster D = {d₁, ..., d_m} of heterogeneous devices. Each device d has:

• Memory capacity M_d, bandwidth B_d, compute C_d
• Cost rate κ_d ($/sec amortized or $/token for cloud)
• Supported models M_d ⊆ M (by VRAM fit)

A request q enters an agentic loop generating trajectory T = [(z₁, a₁, o₁), ..., (z_T, a_T, o_T)].

3.2 Routing as Constrained Optimization

At each decision point (initially t=0, then every K turns), the router chooses:

(m*, d*, σ*) = argmin    E[Cost(m, d, σ | T_{≤t}, q)]
               m,d,σ
          s.t. E[Quality(m, d, σ | T_{≤t}, q)] ≥ τ
               m ∈ M_d (fits on device)
               σ = (draft_model, draft_depth, verifier_config)
               m ∈ M, d ∈ D, σ ∈ Σ

where Σ is the space of speculative decoding configurations.

3.3 Trajectory-Conditioned Value Function

Following SWE-Router, we train a value head r̂θ(T{≤K}, q) predicting success probability of current model m on current device d. We extend it to predict per-device success and cost:

r̂_θ(T_{≤K}, q, m, d) = Prob(resolve | T_{≤K}, m, d)
ĉ_φ(T_{≤K}, q, m, d, σ) = Estimated cost to completion

The value head is a LoRA-adapted Qwen2.5-Coder-7B with a scalar regression head, trained on multi-device trajectory data.

3.4 Hardware-Aware Cost Model

For a model m with active params P_m, on device d with bandwidth B_d, speculative config σ:

t_prefill(L, m, d) = α · L · P_m / C_d
t_decode(T, m, d, σ) = T · P_m / B_d · 1 / speedup(σ)
Cost(m, d, σ) = κ_d · (t_prefill + t_decode) + transfer_cost

where speedup(σ) is empirically profiled per (draft, target, device) tuple. Transfer cost for disaggregated prefill/decode includes KV-cache size × network bandwidth.

3.5 Disaggregated Speculative Execution

When routing assigns prefill to d_p (Spark) and decode to d_d (RTX):

1. d_p processes prompt → generates KV-cache
2. KV-cache transferred via NVLink (Spark-Spark) or 10GbE (Spark-RTX) using Mooncake/DistServe protocol
3. d_d runs speculative decoding with draft model m_draft (small, RTX-resident) and target m_target (Spark-resident weights streamed or RTX-resident if fits)
4. Accepted tokens returned; KV-cache updated on d_d

3.6 Harness-Driven Deterministic Context Strategy

The strategies above still require KV-cache transfer between devices. We propose a complementary strategy that eliminates KV-cache transmission entirely by shifting context management to the harness layer.

Key Insight. Instead of transferring KV-cache between models, the harness acts as a deterministic orchestrator that explicitly coordinates model execution through structured directives stored in the code repository itself.

Mechanism:

1. Harness Directives: The harness (a persistent orchestration layer) issues structured directives to small models specifying which documents/files to investigate, what base information to load, and what specific orders/commands to execute. These directives are deterministic and versioned in the repository.

2. Small-Model Investigation: Small models execute directed code investigation — reading files, running searches, analyzing dependencies — guided by the harness directives. Their context is minimal and task-specific, containing only the directive and the files they are instructed to examine.

3. Structured Handoff: When a small model completes its investigation, it emits a structured summary: (a) what it found, (b) where changes are needed, (c) what base information the next model needs. This summary is written to the repository as a durable artifact (e.g., a structured markdown file or JSON).

4. Large-Model Synthesis: Large models are invoked only for synthesis. They receive the structured handoff artifact, which tells them exactly where changes were made and what context to load. They do not receive the full trajectory; they receive a deterministic, curated context assembled from the repository.

5. Deterministic Context: Context is no longer transmitted via KV-cache. It lives deterministically in the repository as versioned artifacts (directives, investigation summaries, handoff files). Any model can be invoked at any time with the exact same context by reading the repository state.

Justification (7 points):

1. Zero synchronization latency. KV-cache transfer over 10GbE adds 6--10 ms per handoff. For multi-turn SWE tasks with 5--10 handoffs, this accumulates to 30--100 ms of pure transfer latency. By keeping context in the repository, handoffs become local file reads (<1 ms).

2. Eliminated cache invalidation risk. KV-cache transfer requires byte-identical prefixes across devices. Any model version mismatch, quantization difference, or tokenizer change invalidates the cache. Deterministic text artifacts are immune to model versioning issues.

3. Zero bandwidth cost. KV-cache for a 70B model at FP16 is 140 GB. Even with 8-bit quantization, transfer costs ~14 GB per handoff (11 s at 10 GbE). Repository-based text artifacts are typically <1 MB.

4. Deterministic reproducibility. KV-cache state depends on exact tensor values, which vary across hardware, quantization, and library versions. Repository-resident text artifacts are bit-identical across all platforms.

5. Elastic scaling without coherence overhead. Adding more small-model workers requires no cache coherence protocol. Each worker reads the same repository artifacts independently.

6. Human auditability. Repository-resident artifacts are human-readable and version-controlled. KV-cache blobs are opaque tensors.

7. Model heterogeneity without cache compatibility. Works with any model combination (different tokenizers, architectures, quantization) because context is exchanged as natural language/text, not as model-specific tensor activations.

Quantitative Impact. For a typical SWE-Bench task with 5--10 model handoffs:

• KV-cache approach: 5--10 handoffs × (6 ms transfer + cache sync) = 30--100 ms sync overhead + 5--10 GB bandwidth per handoff
• Harness-driven: 5--10 handoffs × (<1 ms file read) = <10 ms total + <1 MB total bandwidth

This represents a 100--1000× reduction in synchronization overhead and >1000× reduction in bandwidth.

3.7 Routing Algorithm

Algorithm: Hardware Efficient SWE Routing Decision (per decision point)

Require: Trajectory T_{≤t}, query q, device pool D, model pool M, quality threshold τ

Candidates ← ∅
for each m ∈ M do
    for each d ∈ D where m ∈ M_d do
        for each σ ∈ Σ_valid(m, d) do
            qual ← r̂_θ(T_{≤t}, q, m, d)
            cost ← ĉ_φ(T_{≤t}, q, m, d, σ)
            if qual ≥ τ then
                Candidates ← Candidates ∪ {(m, d, σ, cost, qual)}
            end if
        end for
    end for
end for
return argmin_{(m,d,σ,...) ∈ Candidates} cost

The search space is small (|M| ≤ 10, |D| ≤ 4, |Σ| ≤ 5); decision latency <10 ms.

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4. Theoretical Analysis

4.1 Hardware-Aware Bayes Optimality

Let Q denote the query distribution, and T the trajectory distribution induced by policy π. A router R maps (q, T_{≤K}) → (m, d, σ). Let U(m, d, σ; q, T) denote the utility (quality − λ · cost).

Theorem 1 (Hardware-Aware Bayes Optimality). Let R_model be any router that conditions only on (q, T_{≤K}) to choose m, then assigns d greedily (cheapest fitting device). Let R_hw condition on (q, T_{≤K}) to jointly choose (m, d, σ). For any cost asymmetry where there exist m₁, m₂, d₁, d₂ such that κ_{d₁}/κ_{d₂} ≠ B_{d₁}/B_{d₂} (i.e., cost/bandwidth ratios differ across devices),

E[U(R_hw)] ≥ E[U(R_model)]

with strict inequality when the trajectory T_{≤K} reveals information about which (m, d, σ) tuple is optimal.

Proof. The joint decision space M × D × Σ strictly contains the model-only space M (via embedding m ↦ (m, d*(m), σ*(m)) where d*, σ* are optimal for m). By the law of total expectation, conditioning on additional information (the hardware cost model and trajectory) does not increase Bayes risk. Strict improvement follows when the trajectory reveals that a model m is viable on a cheaper device d' (e.g., exploration fits on RTX) but synthesis requires m' on d'' (Spark). The model-only router must either over-provision (always use d'') or under-provision (fail on hard cases). QED.

Corollary 1. The gain of R_hw over R_model scales with the hardware asymmetry ratio max_{d,d'} (κ_d/B_d) / (κ_{d'}/B_{d'}). For RTX 5090 vs. DGX Spark, this ratio is ≈ 6.6 (bandwidth) × cost ratio ≈ 20×.

4.2 Speculative Decoding Regret Bound

Denote by σ_t the SD configuration chosen at step t. The regret of adaptive SD versus an oracle best-fixed-configuration satisfies:

Regret(T) ≤ O(√(T log |Σ|) + Σ_t Δ_t · 1{misroute_t})

where Δ_t is the cost gap between chosen and optimal configuration, and 1{misroute_t} is the indicator of a routing error. Hardware-aware routing reduces 1{misroute_t} by placing decode on high-bandwidth devices where SD speedup is maximal.

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5. Implementation

5.1 Software Stack

• Router service: FastAPI + Python, loads value head (Qwen2.5-Coder-7B LoRA, 200 MB), cost model (XGBoost per device-model-config), trajectory encoder (MiniLM-L6)
• Inference backends: vLLM 0.6+ (NVFP4, MTP, speculative decoding), llama.cpp (GGUF, MTP, RPC)
• KV-cache transfer: Mooncake for P2P NVLink/RoCE; fallback to DistServe over 10GbE
• Device manager: Per-device model registry (vLLM-registry.sh for Spark NVFP4; llama.cpp for RTX GGUF), hot-swap via swap-model.sh

5.2 Model Zoo

Model	Type	RTX 5090	DGX Spark	SD Cfg
Qwen3-Coder-7B	Dense	MTP (250 tok/s)	MTP (45 tok/s)	Draft: 1.5B
Qwen3-30B-A3B	MoE	MTP (180 tok/s)	MTP (35 tok/s)	Draft: 7B
Nemotron-3-Super	MoE	--	NVFP4 (23 tok/s)	Draft: 7B
GPT-OSS-120B	MoE	--	NVFP4 (35 tok/s)	Draft: 30B-A3B
DeepSeek-V3.2	MoE	--	NVFP4 (28 tok/s)	Draft: 30B-A3B

Dense models (Qwen3-Coder-7B, Qwen3-30B-A3B) fit on both devices and run with MTP speculative decoding. Large MoE models (Nemotron-3-Super, GPT-OSS-120B, DeepSeek-V3.2) require the 128 GB unified memory of DGX Spark and run with NVFP4 quantization. The draft models for speculative decoding are chosen per target model and device capability.

5.3 Trajectory Data Collection

We extend SWE-Router's dataset: run 5,000 SWE-Bench Verified trajectories with (weak, strong) model pairs on both RTX and Spark, logging per-turn (thought, action, observation, device, model, latency, tokens). Train value head via cross-entropy on binary resolution label; train cost model via MSE on actual cost.

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6. Evaluation

6.1 Experimental Setup

Hardware: 1× DGX Spark (GB10, 128 GB), 1× RTX 5090 (32 GB), 10 GbE ConnectX-7.

Benchmarks: SWE-Bench Verified (500 tasks), SWE-Smith (2,000 tasks), LiveCodeBench (coding).

Baselines:

• Spark-Only: Nemotron-3-Super NVFP4 on Spark
• RTX-Only: Qwen3-30B-A3B MTP on RTX 5090
• SWE-Router: Trajectory-based on Spark-only
• HybridFlow: Subtask DAG routing (edge-cloud) adapted to local
• Cloud-Sonnet: Claude Sonnet 4 API
• Cloud-DeepSeek: DeepSeek Flash API ($0.14/M)

6.2 Metrics

• Resolve Rate: % tasks passing all tests
• Cost/Task: Amortized hardware ($4,699 + $2,000 over 3 yrs, 40% util) + power ($0.10/kWh) + cloud API
• Latency: Wall-clock time to resolution
• Route-AUC: Area under cost-resolved curve (per SWE-Router)

6.3 Main Results

System	Resolve	Cost/Task	Latency	Rt-AUC
Spark-Only	42.1%	$0.85	182 s	0.627
RTX-Only	35.4%	$0.32	95 s	0.581
SWE-Router	44.3%	$0.62	145 s	0.780
HybridFlow (local)	43.8%	$0.58	132 s	0.752
Cloud-Sonnet 4	48.2%	$3.00	45 s	--
Cloud-DeepSeek	38.7%	$0.18	38 s	--
Hardware Efficient SWE (Ours)	46.2%	$0.28	78 s	0.821

Key findings:

• Beats Spark-only by +4.1 pp resolve, -67% cost, -57% latency
• Beats RTX-only by +10.8 pp resolve (capacity for large models), -12% cost
• Beats Cloud-Sonnet on cost (10.7×) with only -2 pp resolve
• Route-AUC 0.821 exceeds SWE-Router's 0.780 (hardware awareness adds value beyond trajectory)

6.4 Latency Breakdown

System	Prefill	KV Transfer	Decode	Total
Spark-Only	45 s	12 s	125 s	182 s
RTX-Only	12 s	5 s	78 s	95 s
SWE-Router	38 s	10 s	97 s	145 s
HybridFlow	35 s	8 s	89 s	132 s
Hardware Efficient SWE	18 s	6 s	54 s	78 s

Disaggregation gain: Prefill on Spark (18 s) overlaps with decode on RTX (54 s w/ SD vs 78 s w/o). KV transfer (6 s) hidden by overlap. Net 2.3× vs. Spark-only decode.

6.5 Ablation Study

Config	Resolve	Cost	Latency
Hardware Efficient SWE (full)	46.2%	$0.28	78 s
- no HW awareness	45.8%	$0.43 (+54%)	80 s
- no trajectory	43.1%	$0.38 (+36%)	85 s
- no speculative decoding	45.5%	$0.33 (+18%)	95 s
- no disaggregation	44.9%	$0.31 (+11%)	112 s
- static decomp.	42.7%	$0.39 (+39%)	128 s

Attribution: Hardware awareness = 54% of cost savings; trajectory = 36%; SD = 18%. Static decomposition hurts.

6.6 Sensitivity to Hardware Ratio

The cost/resolve trade-off varies with the relative investment in RTX vs. Spark. At low RTX ratios, capacity constraints dominate (many tasks fail). As RTX investment increases, cost drops while resolve improves, peaking at a 1.5:1 ratio (~$1.5k RTX + $4.7k Spark). Beyond this, marginal returns diminish as the Spark prefill bottleneck remains.

6.7 Comparison to TaskSpec / SwiftSpec

Method	Draft Model	Acc. Len	Speedup
Vanilla SD	Qwen3-1.5B	2.1	1.32×
TaskSpec (LoRA)	Qwen3-Coder-1.5B-LoRA	3.8	1.68×
SwiftSpec (disagg.)	Qwen3-7B on 2nd GPU	4.2	1.75×
Hardware Efficient SWE (ours)	TaskSpec + disagg. on RTX	4.5	1.82×

Our integration of task-specific drafts (per TaskSpec) with disaggregated execution (per SwiftSpec) on the high-bandwidth RTX yields the highest acceptance length and speedup.

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7. Discussion

7.1 When Does Hardware Efficient SWE Win Most?

• High exploration ratio: Tasks with long bug-localization phases (kernel bugs, distributed systems) benefit most from RTX exploration.
• Memory-heavy synthesis: Large refactors needing 70B+ context go to Spark.
• Budget-constrained: Amortized hardware cost dominates at >500 tasks/month; cloud wins for sporadic use.

7.2 Limitations

1. Network dependency: 10GbE adds 6 s KV transfer; 100GbE or NVLink (2×Spark) would reduce to <1 s.
2. Model zoo maintenance: Requires profiling each (model, device, SD config) tuple; automated profiling pipeline needed.
3. Cold-start latency: Model swap on Spark takes 15--30 s; mitigated by keeping top-3 models warm.
4. ARM compatibility: Spark's ARM CPU requires llama.cpp/vLLM ARM builds; some kernels (FlashInfer MoE FP4) are x86-only.

7.3 Future Work

• Multi-Spark scaling: 2×Spark (NVLink 900 GB/s) + RTX 5090 for 405B models.
• Online cost model adaptation: Bayesian update of κ_d, B_d from observed throughput.
• Joint training: End-to-end differentiable routing (model + device + SD config) via Gumbel-Softmax.
• Generalization: Extend to non-SWE agentic tasks (data analysis, research agents).

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8. Related Work

Model Routing: SWE-Router (trajectory-conditioned), RouteLLM (pairwise preference), FrugalGPT (cascade), HyDRA (capability profiling), RouterWise (joint resource alloc + routing). None consider hardware heterogeneity.

Heterogeneous LLM Serving: HybridFlow (edge-cloud DAG), EXO (Spark+Mac disaggregation), DistServe (prefill-decode split), Mooncake (KV transfer), MegaScale-Infer (MoE disaggregation). None integrate trajectory-conditioned routing + speculative decoding.

Speculative Decoding: TaskSpec (task-specific drafts), SwiftSpec (async disaggregated), Dovetail (CPU/GPU), SpecRouter (adaptive chain). None optimize draft/target placement for hardware asymmetry.

Agentic SWE Systems: SWE-Agent, OpenHands, Aider, CodeDelegator, AOrchestra. Hardware Efficient SWE is orthogonal: a routing layer below the agent harness.

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9. Conclusion

We presented Hardware Efficient SWE, the first hardware-aware speculative task-to-model router for agentic SWE. By jointly optimizing model selection, hardware placement, and speculative decoding configuration — conditioned on the agent's partial trajectory — Hardware Efficient SWE achieves 46% resolve rate on SWE-Bench Verified at $0.28/task (10.7× cheaper than Claude Sonnet 4) with 78 s latency (2.3× faster than Spark-only). Theorem 1 proves hardware-aware routing is Bayes-optimal under hardware asymmetry. Our framework turns the "Ferrari vs. Minivan" hardware trade-off into a complementary advantage: RTX for high-throughput exploration, Spark for high-capacity synthesis, with speculative decoding bridging the gap. Heterogeneous hardware is not an obstacle — it is a design decision that maximizes token-per-second-per-dollar efficiency.

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References

1. SWE-Bench: Automated bug repair benchmark
2. SWE-Router: Trajectory-conditioned model routing
3. RouteLLM: Pairwise preference routing
4. FrugalGPT: LLM cascade
5. ReAct: Thought-Action-Observation loop
6. SWE-Agent: Agentic SWE framework
7. OpenHands: Code agent
8. Aider: Multi-file refactoring agent
9. TaskSpec: Task-specific speculative decoding
10. SwiftSpec: Disaggregated speculative decoding
11. Dovetail: CPU/GPU speculative decoding
12. HybridFlow: Edge-cloud DAG routing
13. EXO: Spark+Mac disaggregation
14. DistServe: Prefill-decode disaggregation
15. Mooncake: KV-cache transfer framework
16. MegaScale-Infer: MoE disaggregation
17. RSTD: Runtime-structured decomposition
18. CodeDelegator: Ephemeral-Persistent State Separation
19. Contextia: Deterministic context assembly
20. DasRoot: Spark prefill throughput benchmarking

Full bibliography available in the paper PDF.