PPAPlace-5000

The official training dataset for PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization, accepted at the 2026 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2026), by Ruogu Chen and Jie Han of the University of Alberta.

PPAPlace paper on arXiv | PPAPlace code and reproduction workflow | Download files | Citation

PPAPlace learns differentiable placement objectives from downstream physical design outcomes rather than relying on wirelength alone. PPAPlace-5000 pairs complete mixed-size DREAMPlace placements with post-global-routing timing, power, and area labels produced by a consistent ChiPBench/OpenROAD flow.

The dataset supports research on post-route PPA prediction, placement ranking, cross-circuit generalization, learned placement objectives, and machine learning for electronic design automation.

At a glance

Training pairs	5,000
Circuits	10 open ChiPBench designs
Placements per circuit	500
Placement representation	Complete mixed-size DEF
Post-GRT targets	WNS, TNS, total power, core area
Paper	Accepted at ICCAD 2026
Paper preprint	arXiv:2608.13790
Compressed download	8.47 GiB

Every pair consists of one final placement DEF and its matching OpenROAD label JSON. samples.csv and samples.jsonl provide a lightweight 5,000-row index with archive paths, labels, generation parameters, and file sizes.

Why this dataset

• Cross-stage supervision: labels come from post-global-routing analysis, not a placement-only proxy.
• Complete placement state: DEFs contain macros and standard cells, which enables full mixed-size spatial features.
• Controlled diversity: placements come from deterministic randomized DREAMPlace configurations and contain distinct macro placements.
• Balanced circuits: every circuit contributes exactly 500 pairs.
• Ready for training: the sample indexes expose the target values and the corresponding archive members directly.

Circuits

Circuit	Placements	Labels	Archive size
bp_be12	500	500	0.20 GiB
bp_fe	500	500	0.17 GiB
bp_multi	500	500	0.90 GiB
dft68	500	500	0.22 GiB
ethernet	500	500	0.18 GiB
isa_npu	500	500	4.97 GiB
mor1kx	500	500	0.44 GiB
or1200	500	500	0.14 GiB
swerv_wrapper43	500	500	0.54 GiB
vga_lcd	500	500	0.70 GiB

Labels and sample index

PPAPlace target	OpenROAD field	Meaning
wns	globalroute__timing__setup__ws	Worst setup slack
tns	globalroute__timing__setup__tns	Total negative setup slack
power	globalroute__power__total	Estimated total power
area	globalroute__design__core__area	Core area

The root samples.csv is directly previewable on Hugging Face. Each row records the circuit, configuration ID, archive member paths, file sizes, DREAMPlace hyperparameters, random seed, and post-GRT labels.

Download

Install the Hugging Face client and zstd:

python -m pip install -U huggingface_hub

Download the complete release:

hf download ValleyC/PPAPlace-5000 \
  --repo-type dataset \
  --local-dir data/PPAPlace-5000

Or download one circuit and the sample index:

hf download ValleyC/PPAPlace-5000 \
  data/bp_fe.tar.zst samples.csv \
  --repo-type dataset \
  --local-dir data/PPAPlace-5000

Programmatic download is also supported:

from huggingface_hub import snapshot_download

snapshot_download(
    repo_id="ValleyC/PPAPlace-5000",
    repo_type="dataset",
    local_dir="data/PPAPlace-5000",
    allow_patterns=[
        "README.md",
        "samples.csv",
        "data/bp_fe.tar.zst",
    ],
)

Extract and train PPAPlace

Each archive expands to one circuit directory. Build the directory structure expected by PPAPlace as follows:

mkdir -p data/ppaplace/dreamplace
tar --use-compress-program=unzstd \
  -xf data/PPAPlace-5000/data/bp_fe.tar.zst \
  -C data/ppaplace/dreamplace

Extract all ten archives under data/ppaplace/dreamplace/. Obtain the matching LEF/design inputs from ChiPBench, then link or copy its per-circuit data as data/ppaplace/chipbench/:

data/ppaplace/
|-- chipbench/
|   `-- bp_fe/                  # ChiPBench LEF/design files
`-- dreamplace/
    `-- bp_fe/
        |-- cfg_001_final.def
        |-- ...
        `-- grt_jsons/
            |-- cfg_001_final_grt.json
            `-- ...

Clone and install PPAPlace, then train on the complete release:

git clone https://github.com/ValleyC/PPAPlace.git
cd PPAPlace
python -m pip install -e .

python scripts/train.py \
  --data_root /absolute/path/to/data/ppaplace \
  --circuits bp_fe,bp_be12,isa_npu,bp_multi,or1200,swerv_wrapper43,vga_lcd,ethernet,dft68,mor1kx \
  --epochs 200 \
  --save checkpoints/ppaplace.pt

How the corpus was generated

For every circuit, the release workflow sampled 1,000 deterministic DREAMPlace configurations. It ran mixed-size global placement, macro legalization, and a standard-cell-only placement pass, followed by the ChiPBench/OpenROAD post-GRT flow. The selector retained exactly 500 candidates with complete DEF/label pairs and different macro placements.

Macros are marked FIXED only during the third pass so standard cells can be placed around that candidate's legalized macro solution. Macro coordinates are not fixed across samples. The final corpus checks confirmed different combined model inputs, non-collapsed spatial channels, and measurable movement by every macro.

The generation and selection tools are published in the PPAPlace repository.

Provenance and license

This dataset is marked license: other because its generated placement DEFs derive from ChiPBench benchmark inputs and no new blanket license is asserted over third-party design material. ChiPBench's top-level BSD-3-Clause notice is reproduced in THIRD_PARTY_NOTICES.md; individual benchmark designs may retain additional upstream notices. DREAMPlace and OpenROAD are generation tools and are not redistributed in these archives.

Please review THIRD_PARTY_NOTICES.md before redistribution. Cite ChiPBench, DREAMPlace, OpenROAD, PPAPlace, and relevant upstream benchmark sources when using the release.

Citation

Please cite both the PPAPlace paper and this dataset:

@article{chen2026ppaplace,
  title   = {{PPAPlace}: Differentiable Cross-Stage Objectives for Chip Placement Optimization},
  author  = {Chen, Ruogu and Han, Jie},
  journal = {arXiv preprint arXiv:2608.13790},
  year    = {2026},
  note    = {Accepted at the 2026 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  url     = {https://arxiv.org/abs/2608.13790}
}

@dataset{chen2026ppaplace5000,
  title     = {{PPAPlace-5000}: Post-Global-Routing Training Data for Learned Chip Placement},
  author    = {Chen, Ruogu and Han, Jie},
  year      = {2026},
  publisher = {Hugging Face},
  url       = {https://huggingface.co/datasets/ValleyC/PPAPlace-5000}
}